Non-volatile memory (NVM) systems make use of an array of NVM cells. An NVM cell is typically an n-channel MOS transistor with an adjustable threshold voltage (VT). There are several known families of NVM cells and several known methods for adjusting the threshold voltages of such NVM cells for either programming or erasing. Such methods include hot carrier injection or tunneling of charge into a ‘storage’ layer or floating gate in the NVM transistor.
The density of NVM cell arrays is one of the key factors in determining the cost of NVM chips. Many circuit and process design steps have been suggested to increase the density of the bits of data in a given NVM array area, including the NAND array architecture (Toshiba, Samsung, San-Disk) and the AND array architecture (Hitachi).
In 1997, Intel introduced the “Strata-Flash” NVM cell, which exhibits double the density of conventional NVM cells. Each Strata-Flash NVM cell is capable of storing two logic data bits. To accomplish this, the threshold voltage of a Strata-Flash NVM cell is adjusted to have any one of four states. These four states are defined as: (1) erased, (2) weakly programmed, (3) moderately programmed, and (4) strongly programmed.
FIG. 1 is a graph 100 illustrating a threshold voltage distribution for one or more Strata-Flash NVM cells. The erased, weakly programmed, moderately programmed and strongly programmed states are represented by curves 101, 102, 103 and 104, respectively. Thus, an erased Strata-Flash NVM cell exhibits a threshold voltage in the range of about 1.5 Volts to about 3 Volts; a weakly programmed Strata-Flash NVM cell exhibits a threshold voltage in the range of about 3.5 Volts to about 3.9 Volts; a moderately programmed Strata-Flash NVM cell exhibits a threshold voltage of in the range of about 4.4 Volts to about 4.75 Volts; and a strongly programmed Strata-Flash NVM cell exhibits a threshold voltage in the range of about 5.6 Volts to about 6.2 Volts.
To read a Strata-Flash NVM cell, the state of the threshold voltage VT of the cell is determined. The result is then decoded to provide a 2-bit read data value. For example, as illustrated in FIG. 1, the erased, weakly programmed, moderately programmed and strongly programmed states correspond with 2-bit binary data values of “11”, “10”, “01” and “00”, respectively.
The Strata-Flash NVM cell requires precise programming of the threshold voltage, such that complex programming circuitry must be provided. In addition, the read circuitry, which must detect four threshold voltage ranges, is also relatively complex. Moreover, even slight drifting of the programmed threshold voltage (e.g., ½ Volt or less) can result in errors.
A completely different type of NVM cell, which is also capable of storing 2-bit binary data values, is the nitride read-only-memory (NROM) cell provided by Saifun Semiconductors, Ltd.
FIG. 2 is a cross sectional view of a conventional NROM cell 200, which includes p-type region 201, N+source/drain (and diffusion bit line) regions 211-212, oxide-nitride-oxide (ONO) structure 220, bit line oxide regions 231-232 and polysilicon control gate (and word line) 240. ONO structure 220 includes lower oxide layer 221, nitride layer 222 and upper oxide layer 223. NROM cell 200 stores two data bits in two separate charge trapping regions 222L and 222R in nitride layer 222.
Charge trapping region 222R of memory cell 200 is programmed by connecting source region 211 to ground, drain region 212 to a programming voltage of about 5 Volts, and control gate 240 to a voltage of about 10 Volts. Under these conditions, electrons are accelerated from source region 211 to drain region 212. Near drain region 212, some electrons gain sufficient energy to pass through oxide layer 221 and be trapped in charge trapping region 222R (i.e., hot electron injection). Because nitride layer 222 is non-conductive, the injected charge remains localized within charge trapping region 222R.
The bit stored in charge trapping region 222R is read by applying 0 Volts to drain region 212, 2 Volts to source region 211, and 3 Volts to control gate 240. Under these conditions, the current conducted by memory cell 200 is dependent on the amount of charge stored in charge trapping region 222R. The current, or lack of current, is sensed by a sense amplifier to determine the state of one bit stored by memory cell 200. Because the read operation is performed in the opposite direction of the program operation, the read operation is referred to as a reverse read operation.
FIG. 3A is a graph 300 that plots the threshold voltages of programmed and erased states of NROM cell 200 for various bit line voltages. FIG. 3B is a graph 301 illustrating threshold voltage distribution for one or more NROM cells identical to NROM cell 200.
Charge trapping region 222L of memory cell 200 is programmed and read in a manner similar to charge trapping region 222R. More specifically, charge trapping region 222L is programmed and read by exchanging the source and drain voltages described above for programming and reading charge trapping region 222R. The state of charge trapping region 222R does not interfere with the reading (or programming) of the state of charge trapping region 222L (and vice versa). NROM cell 200 is described in more detail in U.S. Pat. No. 5,768,192, to Eitan.
Although NROM cell 200 is capable of storing 2-bits of data, it would be desirable to have a NROM cell capable of storing more than 2-bits of data. In order to further increase the density of NROM cell arrays in a given fabrication process, a new architecture is required.
It would further be desirable if such a NROM cell could be laid out in an area-efficient manner, such that the memory density (bits per area) can be increased with respect to a conventional 2-bit NROM cell. It would further be desirable if such an NROM cell could be fabricated using a conventional process.